Khaled Muhammad Walid Nassar2022-05-182022-05-185324https://drepo.sdl.edu.sa/handle/20.500.14154/3240The performance of present VLSI circuits is dominated by interconnect delays. Therefore, there is a great demand to design new placement tools to incorporate performance measures of the circuits. This thesis presents a new method of solving the problem of timing driven placement for standard-cell design style using Genetic Algorithm approach. This problem is solved in an iterative manner using genetic operators. The timing problem is modeled in a path oriented manner, where timing constraints are imposed on total path delays which include both cell and interconnect delays. Improvements upto 17.7% were obtained with respect to clock speed-up of the tested examples compared to the results obtained by area driven placement tools. However, the improvements in timing have resulted in a little increase between 1.4% and 9.1% in the area of the chip after routing. The thesis work is embodied in a program called Timing Driven Genetic Algorithm for Placement (TDGAP)enThesis