Masud-Ul-Hasan2022-05-182022-05-183426https://drepo.sdl.edu.sa/handle/20.500.14154/1116A complete design and implementation of a cell library has been accomplished in this work. This cell library supports a formal high level synthesis framework. The library contains the logic level models of all primitive functions of a Realization Specification Language (RSL). Modular design methodology is employed to support the expandability of basic cells. Examples of a formal adder, multiplier, inner-product and matrix-matrix multiplier are presented. Advisor: Prof. Sadiq M. Sait, Co-Advisors: Dr. Khalid M. Elleithy and Dr. Samir Abdul Jauwad.enThesis