Design and simulation of a current-mode folding amplifier and its application in analog-to-digital converter

Abstract

The applications of CMOS current-mode circuits have increased dramatically. Current-mode signal processing has some recognized advantages over voltage-mode signal processing in low voltage and low power application. Folding is a technique to reduce the complexity of the flash A/D converter by reducing the number of comparators while maintaining a relatively good conversion speed. In other words, in folding A/D converters the number of comparators can be reduced significantly via an analog preprocessing circuit. This thesis deals with design and simulation of a 5 bit new CMOS current-mode folding flash analog-to-digital converter (ADC). A new current-mode folding amplifier is designed to be used as the core block in the folding ADC, which produces a nearly ideal saw-tooth input-output characteristic. The proposed design reduces the complexity of the ADC by reducing the number of comparators, silicon area and power consumption. The functionality of the different building blocks and ADC is simulated using Tanner simulation tools in 0.35μm CMOS technology. The power dissipation of the proposed folding ADC is 1.26mW using a ±1V power supply. Simulation results are in excellent agreement with the theory.