Data-flow expression evaluator for VLSI implementation.

Abstract

This work involves the design and development of a numeric expression evaluating computing systems which can be added as a special purpose slave processor to a host computer. The Data-Flow Expression Evaluator (DFEE) would increase the performance of the host computer in terms of computation speed-up. The expression evaluation system is based on data-flow computing architecture. The architecture is further developed into a highly parallel circular pipelined computing architecture. This architecture is mapped into a Very Large Scale Integrated Circuit (VLSI) design which would be suitable for single chip VLSI implementation.