A C-Based high level synthesis system

Abstract

High-level Synthesis (HLS) refers to the process of translating a high-level specification of the behavior of a circuit into a structural design. The outcome is a net-list of Register Transfer Level (RTL) components, such as ALUs, register and multiplexers. Because of its complexity, HLS is broken into several steps, where a subset of the over-all problem is solved in each step. The steps move the source specification into a target specification, through several intermediate forms. In this work we present a new approach to HLS where the system takes its source specification in any high-level programming language without any restrictions. This is facilitated by the novel idea of using the programming language compiler to produce the first intermediate form in the transformation process. This first intermediate form is the assembly language (AL). The use of the high-level language compiler serves two objectives. The first is the utilization of the optimization carried out by the compiler. The second is to avoid restricting the language to certain data types or control constructs. Due to its machine dependency and complexity. AL is transformed into another form which is machine independent and has simpler syntax and semantics. We refer to this form as Pseudo Assembly Language (PAL). PAL descriptions are used by the system components to produce the intended hardware in an RTL description language. AHPL is used as an RTL description language in the system. The major contributions of this work are the introduction of this new methodology of tackling HLS problem and the introduction of a new heuristic scheduling algorithm based on the path-based scheduling originally presented by R. Camposano in [21].