A VLSI ARCHITECTURE FOR REAL TIME EDGE LINKING.
| dc.contributor.author | AMJAD FUAD HAJJAR | |
| dc.date | 1997 | |
| dc.date.accessioned | 2022-06-01T00:22:24Z | |
| dc.date.available | 2022-06-01T00:22:24Z | |
| dc.degree.department | M.SC. | |
| dc.identifier.other | 6259 | |
| dc.identifier.uri | https://drepo.sdl.edu.sa/handle/20.500.14154/53451 | |
| dc.language.iso | en_US | |
| dc.publisher | Saudi Digital Library | |
| dc.title | A VLSI ARCHITECTURE FOR REAL TIME EDGE LINKING. | |
| dc.type | Thesis | |
| sdl.thesis.level | Master | |
| sdl.thesis.source | SACM - United States of America |