Design and modeling of a real-time RISC processor in VHDL

dc.contributor.authorSyed Asaf Maruf Ali
dc.date1994
dc.date.accessioned2022-05-18T04:56:39Z
dc.date.available2022-05-18T04:56:39Z
dc.degree.departmentCollege of Computer Science and Engineering
dc.degree.grantorKing Fahad for Petrolem University
dc.description.abstractReal-time systems re-characterized by high speed computation and strict timing constraints. Nowadays, powerful processors are capable of executing millions of instructions per second. These high speed processors can be utilized in the design of real-time systems which can benefit from their high performance in order to meet their strict timing constraints. This thesis is concerned with the study of real-time systems and their properties and determining the extent to which these real-time features are supported in currently available RISC processors. Once these features are identified a new instruction set is proposed which attempts to target these features at the instruction set level. The instruction set is optimized for real-time applications by executing instructions in a single cycle and supporting powerful bit manipulation. The instruction set and the data-path are modeled in VHDL (VHSIC Hardware Description Language) at the behavioral level.
dc.identifier.other5182
dc.identifier.urihttps://drepo.sdl.edu.sa/handle/20.500.14154/1571
dc.language.isoen
dc.publisherSaudi Digital Library
dc.thesis.levelMaster
dc.thesis.sourceKing Fahad for Petrolem University
dc.titleDesign and modeling of a real-time RISC processor in VHDL
dc.typeThesis

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