A Systolic Algorithm for VLSI Design Of a Veterbi Decoder

Abstract

The large number of potential applications of the Viterbi algorithm has given a great motivation for a thorough investigation of possible means of implementing it using present state of technology. The drawback of Viterbi decoding, however, is the complexity of the decoder hardware. In this research an algorithm has been exploited further to simplify hardware implementation. A powerful methodology for mapping high-level computations into hardware structure is the systolic arrays. In this research a new systolic algorithm for decoding convolutional codes using the Viterbi maxim likelihood decoding is presented. The new algorithm has been developed in order to design a high-performance, low-cost Viterbi decoder. CMOS design for basic cells for a 1/2 rate Viterbi decoder have been developed. Analysis of the proposed systolic Viterbi decoder has shown that the new decoder is superior to the existing ones in terms of speed, area, and power dissipation. The new design is versatile and has the capability for extending to any R=k/n rate decoder.