Design and Simulation of Multibit Quantum Spatial Wavefunction Switching FET-based Logic and Memories

Abstract

Over the past few decades, integrated circuits (IC) have been able to achieve higher density, and lower power consumption mainly due to the scaling-down of MOSFETs. The requirement for greater information density and faster processing speed created motivation towards multi-bit logic architectures as device scaling reached its limits. Quantum Spatial wavefunction-switched (SWS) field-effect transistor (FET) has two or more vertically stacked quantum-well or quantum dot (QD) layers where the magnitude of the gate voltage determines the location of carriers in each channel. This is used to encode multiple logic states due to carrier transport in mini-energy bands formed in GeOx-Ge/ SiOx-Si quantum dot superlattice (QDSL). The first part of this dissertation evaluates the propagation delay of four-state/two-bit SWS FET-based inverters. The SWS-FET is modeled by integrating the BSIM (Berkeley Short-channel IGFET Model) and the Analog Behavioral Model (ABM). Cadence simulations of propagation delay are used to confirm improvement of performance of the 4 state SWS FET-based inverter as compared to other multi-state logic designs based on conventional CMOS devices. Furthermore, a comparative study is conducted to investigate the effect of lattice-matched II–VI ZnS-ZnMgS quantum well stack as the gate insulator, compared to SiO2 tunnel oxide, on the propagation delay. Therefore, two SWS-CMOS based inverter models utilizing 45 nm technology, one using SiO2 tunnel oxide whereas the other uses lattice-matched II–VI gate insulator, are presented. The smaller density of interface states reduces the fluctuations in the various threshold voltages of the SWS-FETs, and logic using them and improves the device performance. The second part of this work focuses on the design of novel 3-bit D-latch and Flip-flop circuits. The design is based on the 8-state inverter using Quantum Dot Channel (QDC) SWS-FETs in CMOS-X configuration. The proposed design leads to reduced propagation delay, smaller Si footprint, and reduced power consumption. Cadence Simulations of the circuit models are presented to validate the functionality of the proposed designs. The final part of this thesis discusses the fabrication of Quantum Dot Gate (QDG) FETs comprising of Si-SiOx and Ge-GeOx cladded quantum dots. The QDG FET integrates two or more quantum dot layers within the gate region of a conventional n-MOS FET, enabling the formation of intermediate states. These intermediate states enhance the functionality of the devices, allowing for the creation of more efficient logic circuits.