A Layered IP Protection Framework for Integrated Circuits

Abstract

Due to the shift toward a horizontal business model in integrated circuit companies, where semiconductor firms focus on chip design while outsourcing other stages to external vendors, intellectual property (IP) becomes vulnerable to numerous untrusted entities. This shift increases the risks of piracy, cloning, and reverse engineering (RE). To mitigate these threats, hardware obfuscation has been extensively studied over the past decade as a method of safeguarding IP. Hardware obfuscation is a design transformation technique that modifies the original design, making it difficult for unauthorized parties to reverse engineer the IP blocks. By securing the IP with a secret key, the obfuscated design remains non-functional unless the correct key is provided by the rightful owner, effectively preventing malicious use. However, IP obfuscation techniques face several challenges: 1) they often lack scalability for large, commercial-scale designs, 2) they may be insufficient in protecting against emerging functional and structural attacks, 3) they struggle to balance security with design overhead, and 4) they face difficulties in integrating smoothly with various integrated circuit technologies and electronic design automation (EDA) tool flows. In this dissertation, we explore the fundamentals of IP obfuscation, demonstrating its resilience against reverse engineering (RE) attacks. We propose a layered approach to IP obfuscation, combining multiple methodologies to balance complexity and address the vulnerabilities left by individual techniques that only target specific types of attacks. Additionally, we present a practical IP obfuscation framework that seamlessly integrates with the ASIC IP lifecycle, structured ASIC technologies, and the FPGA IP lifecycle. The steps of our proposed algorithm exhibit polynomial complexity, making it scalable for large designs.