A Scalable and Parallel Inductive Learner in Description Logic

Abstract

Inductive logic programming (ILP) is a type of supervised machine learning where the data and the discovered models are described using logic formalisms. The use of such formalisms has strong expressive power at describing a variety of complex concepts and relations. However, when expressive logic formalisms, such as description logic (DL), are combined with large data, the ILP learning performance is greatly reduced. Consequently, real-world applications for ILP learning are limited to small or medium datasets. In this work, we present SPILDL (a Scalable and Parallel Inductive Learner in DL). SPILDL builds upon the DL-Learner, the current state of the art for DL-based ILP learning. SPILDL exploits the parallel computing capabilities of multi-core CPUs to accelerate hypothesis exploration and multiple GPUs for hypothesis evaluation. The result is a scalable and high-performance DL-based ILP learner that can handle and cope directly with large and complex real-world datasets. In addition, a variation of SPILDL known as SPILDL-ES (SPILDL for Embedded Systems) is also proposed. SPILDL-ES is a high-performance DL-based ILP learner specifically designed to exploit parallel computing capabilities of embedded systems hardware. SPILDL-ES handles both ILP learning and monitoring (and controlling) of the embedded hardware in real time. The evaluations of SPILDL and SPILDL-ES on both synthetic and real-world datasets show that speedups up to 360 times faster than the original speed can be reached. It is anticipated this work contributes significantly to the research and development of DL-based ILP systems.