VHDL/FPGA Based Floating-Point Matrix Processing IP Core

Abstract

Our task of building an FPGA board with hardware for integer addition, multiplication floating-point addition and multiplication is a research topic that was well addressed in several previous works. Arithmetic block by reusing and enhancing the fixed-point components such that the cost of floating-point support is a roughly 10% increase in calculating block area. The main challenges are keeping fixed-point performance unaltered, while providing similar floating-point performance, and meeting the area budget. For the floating-point multiplier we had to fuse the rounding stage together with an existing carry-propagate adder – used by the fixed-point modes – by using a flagged-prefix approach in order to reduce propagation delay. Our second proposed solution is for adding subnormal support for the adder and multiplier. The abundant hardware resources on current FPGAs provide new opportunities to improve the performance of hardware implementations of scientific computations requiring FP arithmetic. In this thesis, a Fixed/floating point adder and multiplier have been developed and tested using respectively, Vivado and MATLAB. The proposed cores have been used as basic components for the implementation of a parallel Float point designed for easy the calculation. Results obtained demonstrate the suitability of recent FPGAs for applications based on FP arithmetic. The full proposed designs are proposed, Simulated and Verified with that of MATLAB results. The full proposed designs are proposed, Simulated and Verified with that of MATLAB results. For the future work and perspective, we note: 77 - Reduced area and hardware complexity. - Possibility of using interpolating and folding techniques for further reduction in area and power consumption. - Implementing and testing the proposed architectures and codes on IC technology is recommended as future work. Acquiring experimental results will give credibility and reliability to the obtained results from theoretical simulations. Moreover, it will help encounter the technical problems that may arise in practical implementation of the proposed architectures.