STUDY OF STRAINED SILICON CMOS LOGIC GATES OVER SILICON CMOS LOGIC GATES FOR VARIOUS DEVICE PARAMETERS
| dc.contributor.author | SAAD AL-HUDAIB | |
| dc.date | 2006 | |
| dc.date | 2013-10-17 20:45:15.230 | |
| dc.date.accessioned | 2022-05-29T16:28:47Z | |
| dc.date.available | 2022-05-29T16:28:47Z | |
| dc.degree.department | MSc | |
| dc.identifier.other | 16362 | |
| dc.identifier.uri | https://drepo.sdl.edu.sa/handle/20.500.14154/49981 | |
| dc.publisher | Saudi Digital Library | |
| dc.title | STUDY OF STRAINED SILICON CMOS LOGIC GATES OVER SILICON CMOS LOGIC GATES FOR VARIOUS DEVICE PARAMETERS | |
| dc.type | Thesis | |
| sdl.thesis.level | Master | |
| sdl.thesis.source | SACM - United Kingdom |