Design and Implementation of a RISC Microprocessor

Abstract

The demand for compact, high-speed, and energy-efficient computing systems has made the innovation and advancement of microprocessor designs increasingly vital. This project concerns the evelopment of a fully-featured Reduced Instruction Set Computer microprocessor on an FPGA. A practical instruction set was chosen and used as the basis for a datapath design. Implementation was done on the Cyclone II featured on the Altera DE2 board. Two basic implementations were created based on internal and external memory. The maximum achievable clock frequency was determined to be 63.32 MHz for the internal memory implantation and 44.32 MHz for the external memory implementation. A third implementation featuring a multiplier and a floating-point unit was then developed which achieves a maximum clock frequency of 26.16 MHz and a total power consumption of 41.06 mW. Several programs were written using the new instruction set to test the three implementations, and all produced the expected outputs. However, some areas of the design and testing methodology could be improved.