Back-end design of a formal high level synthesis system
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Saudi Digital Library
Abstract
A complete design and implementation of a cell library has been accomplished in this work. This cell library supports a formal high level synthesis framework. The library contains the logic level models of all primitive functions of a Realization Specification Language (RSL). Modular design methodology is employed to support the expandability of basic cells. Examples of a formal adder, multiplier, inner-product and matrix-matrix multiplier are presented. Advisor: Prof. Sadiq M. Sait, Co-Advisors: Dr. Khalid M. Elleithy and Dr. Samir Abdul Jauwad.