Back-end design of a formal high level synthesis system
| dc.contributor.author | Masud-Ul-Hasan | |
| dc.date | 1993 | |
| dc.date.accessioned | 2022-05-18T04:21:57Z | |
| dc.date.available | 2022-05-18T04:21:57Z | |
| dc.degree.department | College of Computer Science and Engineering | |
| dc.degree.grantor | King Fahad for Petrolem University | |
| dc.description.abstract | A complete design and implementation of a cell library has been accomplished in this work. This cell library supports a formal high level synthesis framework. The library contains the logic level models of all primitive functions of a Realization Specification Language (RSL). Modular design methodology is employed to support the expandability of basic cells. Examples of a formal adder, multiplier, inner-product and matrix-matrix multiplier are presented. Advisor: Prof. Sadiq M. Sait, Co-Advisors: Dr. Khalid M. Elleithy and Dr. Samir Abdul Jauwad. | |
| dc.identifier.other | 3426 | |
| dc.identifier.uri | https://drepo.sdl.edu.sa/handle/20.500.14154/1116 | |
| dc.language.iso | en | |
| dc.publisher | Saudi Digital Library | |
| dc.thesis.level | Master | |
| dc.thesis.source | King Fahad for Petrolem University | |
| dc.title | Back-end design of a formal high level synthesis system | |
| dc.type | Thesis |