VHDL/FPGA Based Floating-Point Matrix Processing IP Core
| dc.contributor.advisor | Dr Zhu Yiqun | |
| dc.contributor.author | SULTAN ABDULLAH JEFYAN ALQAHTANI | |
| dc.date | 2017 | |
| dc.date.accessioned | 2022-05-26T18:02:00Z | |
| dc.date.available | 2022-05-26T18:02:00Z | |
| dc.degree.department | Electronic Communications and Computer Engineering | |
| dc.identifier.other | 35394 | |
| dc.identifier.uri | https://drepo.sdl.edu.sa/handle/20.500.14154/31779 | |
| dc.publisher | Saudi Digital Library | |
| dc.title | VHDL/FPGA Based Floating-Point Matrix Processing IP Core | |
| dc.type | Thesis | |
| sdl.thesis.level | Master | |
| sdl.thesis.source | SACM - United Kingdom |