VHDL/FPGA Based Floating-Point Matrix Processing IP Core

Abstract

Nowadays, digital signal processing systems have been used in a lot of applications across multiple fields; especially those that require real-time and high-speed processing. These application systems commonly require matrix processing such as matrix addition and matrix multiplication. These calculations require special systems, namely FPGAs, which can process data in real-time, using high-speed devices. Therefore, this project aims to write and synthesis VHDL/FPGA designs of reconfigurable (up to 32 x 32) integer matrix addition, integer matrix multiplication, floating-point (double precision) matrix addition and floating-point (double precision) matrix multiplication as well as write their file input/output based VHDL test bench for the purpose of real-time and high-speed processing.